1. Field of the Invention
This invention relates to a semiconductor memory device, specifically to an EEPROM flash memory with electrically rewritable and non-volatile memory cells arranged therein and write voltage setting method thereof.
2. Description of the Related Art
A NAND-type flash memory is known as one of EEPROMs (Electrically Erasable and programmable ROMs), which has features as follows: the unit cell area is smaller than that of a NOR-type one; and it is easy to increase the capacitance. Recently, by use of multi-level data storage scheme, in which one cell stores two or more bits, it has been developed a NAND-type flash memory with a further increased capacitance.
Conventionally, in a normal NAND-type flash memory, one page data write is performed at a time. In this data write, it is basically used such a “verify-write scheme” that a write cycle is repeatedly performed with write voltage application and verify-read for verifying the write data until one page data has been completely written. Further, since it is in need of precisely controlling the data threshold distributions, a “write voltage step-up scheme” is used, in which write voltage Vpgm is stepped-up by ΔVpgm for every write cycle.
The less the step-up voltage Δvpgm, the less the cell's threshold change in one write operation. Therefore, to make the data threshold distributions narrow, and to secure the data reliability, it is required to set the step-up voltage ΔVpgm to be as small as possible. This requirement is strong especially in a multi-value data storage scheme.
However, if the step-up voltage is too small, it is necessary to take a large number of write cycles “n” (i.e., loop number) until a desired write state is obtained. The increase of the loop number leads to write time increasing, so that the write performance will be reduced.
As described above, the step-up voltage ΔVpgm and the loop number “n” are mutually related. To satisfy a write speed specification, it is necessary to decide the upper limit of the number of write cycles, which will be defined as the maximum loop number NLP. In case data write is not yet completed when loop number has reached the maximum loop number NLP, the corresponding page is dealt with a defective one.
Although the maximum loop number NLP and the step-up voltage ΔVpgm are fixedly set, in consideration of them, the initial value of write voltage Vpgm will be trimmed to achieve a desirable write state. In detail, to make the data write possible to be finished within the maximum loop number NLP, a suitable Vpgm initial value will be set.
The Vpgm initial value trimming is usually performed in a built-in self test (BIST) at a wafer stage. The trimming value will be programmed in a ROM fuse circuit together with other, various initial set-up data. Recently, it has been provided such a scheme that the ROM fuse circuit is set in a memory cell array in place of a mechanical fuse circuit (for example, refer to JP-P2002-117699A).